Transistor-level static timing analysis (STA) involves subdividing a circuit design into smaller subcircuits called channel connected components (CCCs), whose outputs drive only interconnect (wires) and transistor gate inputs of other CCCs. Starting from the primary inputs, the signal delays for each CCC that constitute a signal path through the circuit design are calculated and summed using well known static timing analysis methods to identify which paths are critical to the operation of the circuit design. CCCs consist of transistors along with parasitic interconnect elements. The delays of the CCC are most accurately calculated by simulating all the CCC circuit elements using a circuit simulation tool (e.g., SPICE) to obtain the signal delay from each CCC input transition to each CCC output transition that it can cause. However, the accuracy of the delay computation for a driving CCC is limited by how accurately the effects of all load CCCs are modeled when simulating the driving CCC. For instance, as shown in FIG. 1, analysis of driving CCC 10 is impacted by load CCC 12 and load CCC 14.
Transistor-level analysis in other domains such as signal noise and power analysis may similarly divide a circuit design into CCCs and separately analyze the CCCs, summing or propagating different values (e.g., noise pulse magnitudes or power supply current instead of delay). The accuracy of analysis in these domains is similarly constrained by the accuracy of driven CCC load modeling.
One method to account for the effects of the load CCCs 12, 14 is simply to include all circuit elements of the load CCCs 12, 14 in the actual simulation of the driving CCC 10. This would result in a high degree of accuracy of the timing results of a driver CCC 10 at the cost of added simulation time. Since transistor-level STA run-time is dominated by the computationally intensive circuit simulation of CCCs, this option can be prohibitively expensive in most cases. Therefore, other methods of modeling a load CCC input include replacing the load CCC with some approximation (e.g., model load CCC 12′ and model load CCC 14′) such as a single fixed capacitor, a resistor-capacitor (RC) pi model characterized to minimize the error in delay (or some other metric), or the gate terminals of one or more transistors (i.e., the same set of transistor types and sizes present in the load CCC) whose source and drain terminals are grounded. These approaches however suffer from lack of generality and accuracy, as the first two fail to account for nonlinear transistor gate capacitances, and none account for Miller Effect, which is an apparent change in the equivalent grounded capacitance manifested by an ungrounded capacitor (e.g., a capacitor coupling the input and output of a circuit) whose other terminal is also switching. The magnitude of the Miller Effect may itself vary widely depending on the activity of side inputs, which are inputs of the load CCC other than the one whose load is being modeled.
In most applications it is neither possible nor desirable to model all possible loading effects (e.g., as they depend on side input activity), but instead a possible range of simulation results (e.g., minimum and maximum delay calculation) is desired, and calculation of this range of results requires a range of possible loading effects of driven CCCs.